1. Cross-references to Related Patents and Publications
The following references, including patents and publications, describe aspects of a data processing system which are particularly adapted for utilizing this invention.
(a) U.S. Pat. No. 3,710,324 issued Jan. 9, 1973, to Cohen et al, and entitled "Data Processing System"; PA1 (b) U.S. Pat. No. 3,854,126 issued Dec. 10, 1974, to Gray et al, and entitled "Circuit for Converting Virtual Addresses to Physical Addresses"; PA1 (c) PDP-11 Peripherals and interfacing Handbook, Digital Equipment Corporation, 1971.
2. Field of the Invention
The present invention relates in general to data processing systems, and more particularly, to a method and means for expanding the memory capability of such systems with the ability to provide for different expansion memory mapping for CPU and peripherals.
3. Prior Art
A digital computer system normally includes a central processor unit, a random access memory unit and a number of peripheral units. These units may be interconnected by a unified bus, as described in the above-identified U.S. Pat. No. 3,710,324. With unified bussing architecture, all devices, including the central processor, are connected in parallel to the bus. Any device, such as the central processing unit or a peripheral unit, can dynamically request control of the bus to transfer information to another device using an approach based on real and virtual memory addresses, as described in the above-identified U.S. Pat. No. 3,854,126. Thus, the central processor unit can look on its peripherals as if they were locations in memory and can operate on them using the same set of instructions used to operate on memory.
Devices communicate on the unified bus in a master-slave relationship. During any bus operation, one device has control of the bus. The device in control, called the master, communicates with another device, called the slave. Thus, the central processor unit as the master may send control information to a selected peripheral unit which then could obtain the bus as a master to communicate with another peripheral unit as a slave.
The unified bus is used by the central processor unit and all peripheral units connected thereto. A priority structure determines which device has control of the bus at any given instant of time. Communication on the unified bus can be asynchronous and interlocked between devices. For each control signal issued by the master, there is a response from the slave.
In most data processing systems, the address fields of an instruction are of fixed length, that is, each address in the instruction has a predetermined number of bits, digits, or characters to specify a single address location in the memory. The length of the address field is whatever is required to accommodate the maximum memory capacity of the machine. In a unified bus system, each device has a unique address on the bus. Thus, for example, a memory connected to the bus will be assigned a certain set of successive addresses in a block of available addresses. Similarly, other blocks of addresses may be assigned to random access memory units, magnetic disc units, and other peripheral units. However, with such an arrangement, the number of devices including memory units and peripheral units which may be connected to the bus are limited by the maximum number of address bits available in the unified bus of the data processing system.
In a data processing system in which the address field is made up of sixteen bits, it is apparent that there will be only 64K(K=1024.sub.10) available addresses and these addresses can identify directly no more than 64K 8-bit byte locations or 32K two byte word locations. However, to facilitate the storage of information and reduce transfer times, it is often desirable to provide more than 64K byte storage locations in a memory, but to do so requires expansion of the address field or additional coding within the instruction. To solve this problem, a technique known as "virtual addressing" has been used. The term virtual addressing denotes a form of accessing of a central memory wherein the absolute address of information or data to be accessed from the central memory is formed by combining at least one other address. For example, the absolute address could be formed through use of a program address combined with an address indicative of the region of the central memory from which desired information is to be retrieved. However, in a system using virtual addressing, further memory expansion without expansion of the address bits in the bus is still a problem.
In order to facilitate the transfer of programs and data to or from a memory unit, data processing systems normally include some means for arbitrarily dividing the available memory space of any memory unit connected to the unified bus into segments or units commonly referred to as "pages". Each page typically has a fixed number of memory locations; however, from the point of view of efficiency in the use of the available memory space, it is often desirable to use a different paging system in mapping the available memory space for use by the central processing unit than is used by the peripheral units connected to the unified bus. On the other hand, it is absolutely essential that the data processing system control the allocation of available memory space in such a way as to avoid any possibility of confusion in the address of a selected location in memory by the central processing unit and a given peripheral unit.
Therefore, the object of this invention is to provide a memory expansion unit which may be used with a unified bus data processing system of the type described.
Another object of the present invention is to provide a data processing system employing virtual addressing for address expansion to which additional directly-addressable memory capacity may be added without expansion of the address field.
Yet another object of the present invention is to provide a data processing system of the type described including a memory expansion unit having the capability of providing for different expansion memory mapping for the central processing unit and the peripherals attached to the unified bus and further to provide for different page sizes.